Introduction
In this blog I explain about D flip-flop. It is a type of flip-flop which mostly used in memory cells in computer. This store 1 bit of data in it. It has a one input pin called 'D'. The input data is copied to the output. The data is stores in it until a power failure occurs.
What is a flip-flop ?
A flip-flop is a 1 bit digital data storage unit. The latch is also done this work. But the difference between latch and flip-flop is that, In flip-flop the data input is read only when there is a clock present. So a clocked latch is called a flip-flop. The clock is a enabling mechanism. That is the data only passes to the latch when a active clock is present in clock pin. The clock triggering is different types. Edge triggering and level triggering. In level triggering the data passes in the entire active clock pulse. But in the edge triggered flip-flop the data passes only at the active level shifting instant. So, the edge triggering is used in most of the digital circuits.
The circuit diagram is given below,
Circuit Explanation
Consider the above circuit diagram. In the above circuit diagram the 2 transistors make the latch circuit. It's working is same as latch which given in my previous 'LATCH BLOG'. The extra components are the three resistors and one capacitor and one transistor. These are used to form the edge triggering clock circuit. The transistor used to pass the input data when there present a +ve voltage in it's base. The base voltage is provided by the external clock. The clock signal is just an enabling signal, here it is +ve triggered. The capacitor and the resistor in the transistor base is used to convert the input square wave signal to sharp spike signals. So it is a passive differentiator circuit. This differentiator circuit makes this to be an edge triggered flip-flop. If we not use this differentiator and only use the pass transistor then it work as a level triggered flip-flop. These all are explain very well in the given video.
D Flip-Flop Working
We already discussed the latch working in my previous 'LATCH BLOG'. Assume that the latch output Q is at logic '1'. So now we apply a logic '0' (Gnd) signal to the 'Data In' to change the stored data to logic '0'. Now we apply a +ve clock pulse in the clk pin. So, in the transistor base get a +ve spike, so it get ON and short the GND to the latch input. So the latch output Q changed to logic '0' and it store it. Now we apply a +ve signal in the 'Data In' pin. Now apply a +ve clk signal in the clk (before it, give a -ve signal for discharge it). So the pass transistor collector-base junction get forward biased and so a small current flows from base to collector. This trigger the latch and the latch output Q is changed to logic '1' state. This is the working of discrete D flip-flop using transistors. The truth table is given below.
If you like it please support me.
In the given video, given the working of D flip-flop.
If you like it please support me.
For more about its making process, Please visit my instructables page. Link given below,
For discrete T flip-flop, visit my new blog. Link given below,
Thank You........
Hi I'm using your schematic for a project im doing. In LTSpice I have a voltage source with the parameters "PULSE (0 5 .5s 1ms 1ms 1s 2s)" to replicate a clock. Everything works however the flip-flop you've made seems to react to the rising edge of the clock. Is there a way to use this schematic to work with the falling edge or should I change the parameters of the clock?
ReplyDeleteI think, use a PNP transistor instead of NPN transistor (Q3) at the input side. It is just a possibility. You try this way. OK. Don't forgot to change the connection of R5(220K) from ground to the VCC.
DeleteOK.
Thank You.
That worked! Thank you so much. I am using your d-flip flop to create a 4-bit serial-in parallel-out shift register using only transistors. If you have any advice for this project I will be open to it! Thank you.
DeleteGood. But there is one problem. This design not good for high speed circuits. If you need to improve the speed, then it need modifications. I designed this circuit with minimal components. So its speed get reduced. OK. If you design the shift register for demonstration purpose then it work fine. OK.
DeleteThank you.
How did you get this to work for the shift register? Did you use 4 bjts? where to place the 4th?
DeleteI am trying to create a Serial-In-Serial-Out Shift register by using these D-Flip-Flops. How do I go about doing it? How exactly do I cascade them? What are the changes that I should make?
DeleteI don't understand why the third transistor is in reverse. It obviously works though.
ReplyDeleteHi,
ReplyDeleteI need a high speed discrete flip flop. , 88-108 MHz.
Is it possible for you to design?
What Is A D Flip-Flop ??? (Using Discrete Transistors) >>>>> Download Now
ReplyDelete>>>>> Download Full
What Is A D Flip-Flop ??? (Using Discrete Transistors) >>>>> Download LINK
>>>>> Download Now
What Is A D Flip-Flop ??? (Using Discrete Transistors) >>>>> Download Full
>>>>> Download LINK wr
Excellent information.
ReplyDelete-------------------------------------
I work with fiberglass roofing panels